Muzaffer Kal
Muzaffer Kal
I'm trying to generate SC output from Verilator (Verilator 5.013 devel rev v5.012-63-g3454641) with verilator --debug --sc --timing -Wno-lint --top ce $^ I have a generate for loop ala: generate...
I'm using existing IP from PULP which has the following construct: task set_ir(input logic [IrLength-1:0] opcode); logic opcode_unpacked [IrLength]; // check whether IR is already set to the right value...
Hi, I'm using some Pulp code which has the following construct in https://github.com/pulp-platform/riscv-dbg/blob/master/src/dmi_test.sv. When I run this test, I get %Error-UNSUPPORTED: dmi_test.sv:182:45: Unsupported: randomize() 'with' constraint 182 | rand_success =...
Hi, I'm trying to adapt some of the https://github.com/pulp-platform/riscv-dbg/ files for my purposes. In there there is a declaration of a class with a typedef inside: ``` class riscv_dbg #(...
### Bug description If a network returns multiple outputs, the forward hook at crawler.py:181 crashes because the out parameter is a tuple and not a tensor so it doesn't support...
fix crash with multiple output networks # What does this PR do? Closes # (issue) ## Before submitting - [x] Was this discussed/approved in a Github [issue](https://github.com/frgfm/torch-scan/issues?q=is%3Aissue) or a [discussion](https://github.com/frgfm/torch-scan/discussions)?...
Hi, Currently the only FP8 support is E5M2. How complicated would it be to add E3M4 and E2M5 support? Can I make a contribution to some organization to get these...
Hi all, I need an FMA block that can do BF16*int8+int8. Is there a way to configure this option in the IP? If not, what are the minimum conversions I...