Tomasz Motylewski comments

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                                            Tomasz Motylewski

Interfacing to Xilinx Vivado block design environment

Hi Dan, Thanks for thoughtful evaluation. - default_nettype : fixing vendors code is not possible in all situations. Some source code may even be encrypted. No, I have not filled...

Interfacing to Xilinx Vivado block design environment

As for naming: I think I slowly start understanding that there are at least following modes: - wishbone classic: assign ACK_O = CYC_I && STB_I && ! busy; - wishbone...

Interfacing to Xilinx Vivado block design environment

Hi Dan, I will run Monday some tests to see whether Vivado allows connecting different interfaces, or interfaces with different version IDs. I tend towards simply using opencores.org : bus...

Interfacing to Xilinx Vivado block design environment

OK, it looks that Vivado block design GUI connects interfaces only when the complete name including version matches. I have decided to use the following names: ``opencores.org:bus:wishbone:B3`` ``opencores.org:bus:wishbone:B4`` (most interfaces)...

Support LitePCIe on Lattice ECP5 SERDES (with open toolchain)

I would like to sponsor further development of a free ECP5-PCIe core with free Verilog toolchain for LFE5UM(G) (ECP5UM5 or ECP5UMG) with: - now - one LFE5UM-45F-VERSA-EVN(G) eval board (costs...

Support LitePCIe on Lattice ECP5 SERDES (with open toolchain)

Hi @whitequark , I am fully aware that my meager 800 EUR+board was just an incentive, bait for someone who wanted to do it anyway as a hobby project, to...