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SystemVerilog FSM generator

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Added a newline character before each moore output in dot visitor as to improve readabillity of complex state machines. Don't know if you like it aswell, but thought I would...

In case of a state without transition condition but with mealy outputs; the parsing is failed. As an example, you can see the DEFAULT state on following code. ```yaml transitions:...

Hi Mohammed, I found this tool very interesting. But I am new to python and yaml. Is there a document that describes the steps that I need to setup the...