Tim 'mithro' Ansell

FYI @dalance has a System Verilog Language server at https://github.com/dalance/svls which comes from https://github.com/dalance/sv-parser which does very well at https://symbiflow.github.io/sv-tests

I was thinking something like this; 

I don't quite understand what `ci` mode is for? How is it different from the normal mode?

You'll probably want a regex for URLs; - See http://stackoverflow.com/questions/3809401/what-is-a-good-regular-expression-to-match-a-url - http://stackoverflow.com/questions/161738/what-is-the-best-regular-expression-to-check-if-a-string-is-a-valid-url - https://mathiasbynens.be/demo/url-regex - https://gist.github.com/gruber/8891611

We have had comprehensive set of tutorials in the wiki for at least a couple of years now. See the page at https://github.com/timvideos/litex-buildenv/wiki/HowTo-LCA2018-FPGA-Miniconf-VexRiscv-Renode or https://github.com/timvideos/litex-buildenv/wiki/HowTo-FuPy-on-iCE40-Boards example. If you know what...

Hi @mistotebe Thanks for your patch! It looks like it currently isn't pep8 clean, can you please fix that? ``` === Running pep8 on files pep8 q.py setup.py test/test_basic.py q.py:287:80:...

Generally looks good. Can you think of any way to add a decent test for this functionality?

@abadger - If you have time, can you talk a look at this pull request? As mentioned I'd like to add some tests before I merge this functionality though.

@Schabernack - If you could write a test or two for this, I'll merge and do a release?

This project is mostly unmaintained. I had hoped to have the time to be able to do the maintenance from @zestyping but was never able to beyond some very minor...