Tim 'mithro' Ansell

@shakouri - Please report the systemverilog issues to the issue tracker @ https://github.com/chipsalliance/yosys-f4pga-plugins/issues

You might want to consider [Surelog](https://github.com/chipsalliance/Surelog) + [UHDM](https://github.com/chipsalliance/uhdm) as an option for [parsing SystemVerilog for usage with Yosys](https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/). The team at @antmicro has recently been focused on making the Surelog+UHDM...

@Dolu1990 - You might find using [DFFRAM](https://github.com/AUCOHL/DFFRAM) as an alternative solution.

@Dolu1990 - You should know how to build a 4R 2W out of DFFRAM blocks, same thing we do as in FPGAs -- https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html :-)

@Dolu1990 - You should also log a feature request on the DFFRAM repository. BTW If you are doing this as part of funded research, funding AUC is extremely cheap.

In a somewhat related note -- Antmicro was talking about a tool called "Visual System Designer" a few months back. See the following links; * https://riscv-europe.org/media/proceedings/plenary/2023-06-06-14h15-Michael-GIELDA-slides.pdf * https://www.youtube.com/watch?v=-Ts43wiQ640 and https://www.youtube.com/watch?v=6XtnTkCRrww...

@bunnie - Do any of your tests make sense to incorporate in this upstream repository?

FYI - @kgugala @mgielda @pgielda

@mateusz-holenko who did the Renode and DeviceTree generation parts might have opinions. @xobs who did the SoCDoC and a bunch of Rust & SVD related generation might also have opinions.

@xobs / @bunnie - As likely users of this, could you review it?