Matute

This test is not needed since all tests will implicitly test POR.

### Description The sival autogen flow should filter out testpoint marked as `si_stage: None` since that indicates the test is not suitable for fpga or silicon, and can only be...

[dv/rstmgr] Apply different reset kinds where applicable

7

Most unit tests use the default apply_reset kind argument. The rstmgr unit has both AON and non-AON domain components, so the apply_reset distinction is important. One way to exercise it...

[dv/csr_utils] Fix handling of reset for rstmgr alert_info_ctrl

4

### Description When attempting to enable read checks for alert_info_ctrl in the rstmgr scoreboard we get a mismatch soon after a reset. On reset only bit zero of alert_info_ctrl should...

[hjson,format] Re-format some hjson files per style guide

1

Deals mostly with indentation and description fields.

### Description A big breakage of flash_ctrl tests performing flash_prog was introduced in #22804. That PR missed running a full regression, or it would have found these breakages. My apologies....

[dv,flash_ctrl] Fix initialization of secret pages

3

### Description The flash_ctrl block level environment initializes pages 1, 2, and 3 with random data with scrambling and ecc configured per the update_secret_partition function at https://cs.opensource.google/opentitan/opentitan/+/master:hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv;drc=30d7e787c753caaa03fe68a4a70da1bbcbc1d96f;l=1452. This is done...

[dv/clkmgr] Test different rst_io* and rst_root_io*

1

### Description clkmgr has rst_io_ni, rst_io_div2_ni, and rst_io_div4_ni. Similarly it has three rst_root_io*. The testbench hooks them all to the same interface. We should hook these to different interfaces and...

[rtl,clkmgr] Declare clkmgr at D3

3

The justification is added as a comment in https://github.com/lowRISC/opentitan/issues/22482. Fixes #22482

[doc,pwrmgr] Declare pwrmgr at D3

1

The justification is added as a comment in #22487. Fixes #22487