mattfel1
mattfel1
The first time I tried writing a 3D convolution where I MemReduce each slice of the cube into a 2D result, I wrote it this way: ``` val lineout =...
What is going on here? I was looking at Stefan's lenet and there are strange things with c2_RF: There are 25 accesses to c2_RF, each parallelized by 4. In the...
compacting fifo is an expensive version of the legacy fifo used for lane-enabled accesses and when any lane can touch any bank. It probably makes sense to have the same...
There are some mods and divides in the critical path of compacting fifo operations. For now I squashed them into single cycle ops but we should probably tell the compiler...
This is just a thing that would be nice to have: ``` @struct case class comp_acdc(index: UInt8, dc: UInt8, ac: UInt8 ) ... val ac_dram = DRAM[UInt8](64) ... val sram...
Seems like the IIof the second FSM in BasicFSM is not capturing the fact that the next state is dependent on the operations that happen inside of the fsm body....
In SimpleTileLoadStore, I had the following: `Accel{` ` val b1 = SRAM` ` Foreach(N by 1 par 2) { i =>` ` b1(i) = // something` ` }` `}` `...
Shouldn't this code throw an exception? It is making it through codegen but the sram has one bank and two writers that happen at the same time. ``` @virtualize def...
In SPMV_CRS (checked into develop now in MachSuite.scala), I think there is an issue with the gather. I see 16 addresses get sent to Fringe, and then I see those...