Matt Liberty
Matt Liberty
abandoned
Fixed upstream
Issues or PRs should be filed with https://github.com/parallaxsw/OpenSTA if still relevant. This is effectively a fork (though not strictly for historical reasons).
Isn't "Nets are created or destroyed" covered by "Net connections change"?
You've lived an easy life then. I suggest reading https://vlsicad.ucsd.edu/Publications/Conferences/377/c377.pdf
The run.sh seems to be running a whole bunch of steps. Is this the right script?
Sorry I'll take a look again.
I see that @precisionmoon added Verilog2db::processUnusedCells which is what is instantiating your extra block. The intended use model is for operator mapping where we get uninstantiated alternate implementations of operators...
I see it is marked keep_hierarchy : ``` (* keep_hierarchy = 1 *) (* src = "inputs/bp_multicore.sv:83614.8" *) module \bp_me_stream_pump_control$bp_multicore.cc.y[0].x[0].tile_node.tile.core.fwd_xbar.sink_comb[0].pump_control (clk_i, reset_i, header_i, addr_o, ack_i, last_o, first_o, critical_o); ```
That would make sense. I believe there is one we use to know about the operator we are swapping.