Lukas Chrostowski

Add a check for odd path widths, e.g., 499: https://github.com/KLayout/klayout/issues/1095

from KLayout to INTERCONNECT, the LC parameter is not transferred to the schematic.

ebeam_wg_strip_1550 CML problem

2

Component needs to be deleted or fixed in the CML. 

Implement something similar as in phidl, namely adding the ability to automatically compress layouts consisting of tons of test structures. using: https://github.com/secnot/rectpack similar to: https://github.com/amccaugh/phidl/blob/master/phidl/geometry.py - input: a bunch of...

For slightly offset pins (less than 2X min bend radius), automatically insert an S-bend rather than two too-small bends.

Adiabatic taper

1

Create an "adiabatic taper" based on the paper: https://doi.org/10.1364/PRJ.2.000A41 This requires an implementation of equation 2 which can be done in KLayout: theta (x) = lambda / 2 W n_eff...

3D view from layout

1

Generate a 3D view based on extruded GDS. e.g., packages: http://pygeo.sourceforge.net/distinguishes.html

- Identify a mechanism for the user to select the model accuracy. This could be, for example, - in the layout PCell parameters - in a simulation configuration window, where...

Objective: run a 3D-FDTD simulation for a KLayout component to generate the S-Parameters; automatically import them into INTERCONNECT to enable circuit simulations. Concept based on 2014 UBC-Mentor Graphics project by...

if wg_width > 0.5, issue warning about bend radius... perhaps require parameterized data for the optimal bend vs. radius.