Lysdal
Lysdal
It seems it isn't per the text, but in my project I can't seem to get it running - would I be right in assuming that this is because the...
Can be replicated using [apply_force.txt](https://github.com/wiremod/wire-fpga/files/12135803/apply_force.txt) FPGA chip Debugging shows that this happens: `nodeQueue = {1,3,2,5,}` when we put down 1 as our loop detection node `nodeQueue = {1,3,4,5,}` 4 iterations...
Like with E2, but something FPGA related. Maybe logic gates circling their head?
The current algorithm is queue based, which worked great when loops weren't a thing. As execution has grown more complex, it went from worst case n², to in complex case...
Currently the input field for constant Vector and Angle values validate it is right, but it doesn't show any text if it's invalid. It could be a bit confusing, even...
FPGAs limit performance based on average server time (rolling average). This works fine for the most of the time, but servers can spike for some time, crashing FPGAs because they...
When a chip is uploaded, it is first validated, compiled, and then executed. The validation step is to make sure that the player doesn't send some garbage that will just...
It makes enough sense logically that it should be a feature - two inputs with the same name should just update based on the same input. This would make some...
My idea for this is that you can define HiSpeed inputs that are assigned to memory ranges (in the FPGA HiSpeed addressing space), and then those HiSpeed links can be...