circt
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Circuit IR Compilers and Tools
Remove the `-mem` suffix in the `ignore-read-enable-mem` option of the `HWMemSimImpl` pass. "Read enable" should be unambiguous already. Note that this does not change the corresponding firtool flag, so no...
When having a module with two instances with the same symbol names, no error shown complaining about symbol redefinition, i.e., `circt-opt` on the following code does just parse, verify, and...
Inspired by the PR to print IR after specific passes, I thought people might also be interested in this patch I use sometimes for debugging. This adds an experimental pass...
`CreateSiFiveMetadata` will not emit information about modules annotated with `SignalMappingAnnotation`. https://github.com/llvm/circt/blob/2e87750c597abe0a12c5b94cb00f441159203e17/lib/Dialect/FIRRTL/Transforms/CreateSiFiveMetadata.cpp#L332 This might have been copied from the original pass implementation. This annotation might not ever actually appear in the...
Specifying various `-preserve-values=` options (default is 'none' presently) does change the option but not as expected: ``` $ ./bin/firtool ./test.fir -verbose-pass-executions -preserve-values=none |& grep -o "drop-names{preserve-values=[^}]\+}" drop-names{preserve-values=named} drop-names{preserve-values=named} drop-names{preserve-values=named} drop-names{preserve-values=named}...
Noticed this while adding statistics, here's a small test case `names-cse.fir`: ```firrtl circuit Names: module Names: input i: UInt input j: UInt output o: UInt wire w: UInt wire w2:...
I am mostly curious if this is what is supposed to happen, and there doesn't appear to be any tests of this behavior. A don't touch on an instance's port...
Using a clone from 53a60c651c6f235d628a8fc6b1ceec0a3d94319b After installing the python bindings through a `pip install .` in `lib/Bindins/Python`, I tried the example from https://circt.llvm.org/docs/PythonBindings/#trying-things-out and got the following error: ``` $...
This a WIP implementation of a scheduler for the `SharedOperatorsProblem` using a CP-SAT solver, through OR-Tools. The formulation/model is the [Resource Constrained Project Scheduling Problem](https://python-mip.readthedocs.io/en/latest/examples.html#:~:text=The%20Resource%2DConstrained%20Project%20Scheduling,required%20amount%20of%20different%20resources.) (but I do not use...
This PR is related to #3441. I want to discuss a potential implementation of a System Verilog Streaming operation. Rationale ==== The SV streaming operator comes in two different flavors:...
