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Circuit IR Compilers and Tools
Fixes #7542. @FanShupei Could you try if this PR fixes the issue?
This changes the OM dialect Class/ExternClass to use a terminator operation similar to hw.output. The ClassFields and ClassExternFields operations use a custom printer/parser to provide a syntax similar to hw.module...
Run canonicalization before LowerLayers in order to optimize things which are difficult to do after layerblocks have been converted to modules. The conversion to modules means that many trivial canonicalizers...
Dear @maerhart @fabianschuiki , When lowering `SV` to `Hw` Dialect, there is a stack dump. Driver: circt-verilog %s ``` module top(); typedef struct { int a; int b; } ms_t;...
See #6523 The conservative restrictions of comb canonicalizers across blocks are hindering many optimizations at various places. E.g., the `sv.initial` mentioned in above issue, but also the HW/Comb/Seq/LLHD produced by...
This was uncovered while trying to move verification statements automatically into layers in Chisel. I'm seeing a missed opportunity for eliminating a `circt_chisel_ifelsefatal` intrinsic. Consider the following where the assertion...
This patch lowers `scf.parallel` op to Calyx by invoking multiple `calyx.component`s in parallel. I'm not pushing test files for now because some required features are not upstream yet. But I...
The Chisel's Definition API generates modules that are not instantiated, whose reset cannot be inferred properly. Remove them before InferResets pass to resolve it. See [chisel#4292](https://github.com/chipsalliance/chisel/issues/4292)
In order to create a branch that compiles with LLVM 19 this PR sets a LLVM commit to 19.1.0-rc1 in release/19.x (the branch cut from firtool 1.81.0 since it uses...
