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                                            SITAO LIN

Regarding the loss of active reset behavior of Reg or being overridden by RegInit.

Thank you, I understand. It's unfortunate that Chisel does not support initial values like System Verilog.

Semantic Inconsistency in Intermediate FIRRTL File During Compilation: Incorrect reg Emission Instead of node and Loss of Memory readUnderWrite Behavior

Thank you very much for your response. Regarding (3), I no longer have any doubts, but I am still confused about (1) and (2). In fact, I observed the bugs...