Leon Woestenberg

icon indicating a website link http://www.sidebranch.com/

icon company Sidebranch icon location Switzerland icon location Freelance embedded systems consultant targeting interesting projects with bare-metal, RTOS, Linux, kernels, drivers, SoC, PCI Express and FPGA technologies.

Results 18 comments of Leon Woestenberg
trafficstars

Feature: translateWith() for Stream(Fragment())

BTW, I am having a hard time interpreting the `.~~` and `_` here, but the code works perfectly :)

Feature: translateWith() for Stream(Fragment())

> use translateWith might be better option Do you mean we should also add translateWith() (instead of ~~) for Stream Fragments? And that it looks clearer in code?

Feature: translateWith() for Stream(Fragment())

As the previous remarks were confused about ~~, let me re-summarize this issue: We have wihTranslate for Stream(), but this does not work for Stream(Fragment()).

Feature: translateWith() for Stream(Fragment())

I don't know -- could be :) I think it should be the same interface as Stream .withTranslate() but now for the Fragment data (i.e. not the last signal). The...

facility to enhance pcie dma.

Can you explain what this issue is about? Most FPGAs only have the lowest three PCIe layers (up to including the TLP transaction layer) as a hard-IP block, everything else...

facility to enhance pcie dma.

Are you interfacing against PG195 or replacing PG195 with a SpinalHDL implementation? I am asking because I have co-developed that block. I could help on both approaches.

facility to enhance pcie dma.

Nice work. My question is: Are you... 1) ...replacing PG195? XOR 2) ...interfacing with PG195? Thanks

Weird bugs meet with fb2CG and Vivado 2023.2

For a newcomer to HDL, kudos for tracing the issue back. I wonder was this issue ever reported to AMD/Xilinx? We probably need a minimal piece of Verilog code demonstrating...