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leonardt
A Python package for testing hardware (part of the magma ecosystem)
The main readme says that you can work with internal signals. It provides an example for calling .expect(). How can I print the internal signals? The line https://github.com/David-Durst/aetherling/blob/26ccb851cf179ed8e45a0e21fc76c3b95c2085d7/tests/test_bitonic_sort.py#L28 fails: ```...
**This is a low priority feature request.** The names of circuit instances are often quite different and unintelligble relative to the names of the variables that the instances are assigned...
Added a bunch of actions like if_, while, scan, we should add docs for all those.
I think with the new control flow and conditional features, we should be able to implement these. We should create some tests/examples showing how this is done in fault.
Add the ability to specify properties inline with a magma module definition and/or a peak specification.
The SystemVerilog targets actually don't compile the Verilog testbench unless you call `compile_and_run` instead of just `compile`.
If you wire the clock parameter to a testbench, I would assume that it works without having to do anything special to the clock. However fault does not initialize the...
The tutorial says `compile_and_run` will compile my module. However, I also needed the below lines to actually compile my module https://github.com/David-Durst/aetherling/blob/6de744252d7b5becb9be41e7b452a7e21a8a1fc5/tests/test_rshift.py#L24-L26. Should the tutorial be changed? Am I using the...