lekcyjna123
lekcyjna123
Recently we added new functionalities to transactron: - single caller methods - simultaneus transactions - ready_function We should extend "Advanced concepts" [section](https://kuznia-rdzeni.github.io/coreblocks/Transactions.html) with information about those features.
Here is a PR to merge branch with implementation of vector extension. As for now I am going to merge here all already open PR's related with vector extension. List...
We don't have support in regression PySim for checking if core reported illegal instruction exception. I started by mistake a test with vector instructions on core without vector extension and...
To generate traces from cocotb benchmarks we need to pass `-t` flag, but additionally we have to manually clean the `test/regression/cocotb/build` directory, so that verilator files will be generated once...
It would be nice to integrate generation of verilog core with scripts to run benchmarks and regression, so that they can check if given configuration contains all extensions which are...
Today I have synthesised coreblocks (with vector extension) in quartus and surprisingly I get 66 MHz Fmax for the slowest FPGA fabric (similar settings in nextpnr get Fmax ~45MHz). Analysing...
Currently each unit test is parameterized using two values important from running test case: seed and test_number. First set seed for random generator and second said us how many iteration...
Actually `auto_debug_signals` can not collect signals from `ModuleConnector` (probably because of using `args`/`kwargs`) so it has to be either investigated why `auto_debug_signals` can not get needed signals, or a `debug_signals`...
On the beginning of the project we did an assumption that decoding in FU will consist of two steps. First we decode `exec_fn` to internal one-hot representation and next we...
Currently we have implemented a MultiportFifo, that gives very strong guarantees: - all elements are in time order - always maximum subset of methods is usable But this comes at...