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kuznia-rdzeni
RISC-V out-of-order core for education and research purposes
Extend CSR component with a wrapper which will provide a possibility to connect 2 or more small CSRs into a one bigger CSR. The goal of these changes is to...
This PR ports from #395 a `def_one_caller_wrapper`. Function which is a syntax sugar for introducing a Fifo which collect all incoming data and pass them to the one_caller method. Examples...
Try to find a way to add support for FMADD and FMSUB without adding a new source register into main pipeline.
Extend decoder by adding support for all instructions from F extension except FMADD and FMSUB (these two instructions has 3 source operands and 1 output operand).
Analyse available in internet open source cores. Choose one and integrate it with Coreblocks. Check if we are able to use our current synthesis scripts to synthesise core with F...
As one picture is supposedly worth a thousand words:  The task is to investigate and make sure this doesn't happen again.
*issue not valid before: merge of #493* When side effects are disabled and core is flushed, long instructions such as division or memory read requests are still executed. It would...
Some time ago, we made the decision to not use the physical register 0, so that the 0 can be used for two things: * mark that an operand is...
I create this issue, to allow for brainstorm how to implement non blocking `if` in transactron. Lets take: ```py with Transaction().body(m): with m.If(m, cond): method(m) ``` In current implementation we...
This PR utilizes `def_helper` mechanisms to create a nicer API for using transformers. Following changes in interpreting the function arguments of the transformer classes are made: * The module parameter...
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RISC-V out-of-order core for education and research purposes