coreblocks
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RISC-V out-of-order core for education and research purposes
It would be nice if the arrows in the benchmark bot comments were colored, to signify changes for better or worse. This essentially requires two things: * Knowing which metric...
This PR changes some 2-FIFOs (mostly in the scheduler) into `Pipe`s. Pipes have more combinational connections than FIFOs, but use less resources. The purpose is to validate the usefulness of...
Closes #599 Implements priv spec core internal interrupt controller operating on CSRs. Details in docstrings. Depends on #652 , needs rebase to reflect changes and clean-up from it after it...
Right now if an exception is raised during the execution of benchmarks, the core will jump to 0x0 (the default value of `mtvec`) and will keep executing the code. This...
Since the fetch unit will be able to deliver multiple instructions per cycle soon, we could use that to implement instruction fusion. We could start by simply looking at two...
The Zicond extension extends the architecture with conditional instructions, which allow to create code with less branches. It's probably the best to implement this in ALU.
There is a need to move stuff around to make things more intuitive for newcomers (and others). Some problems in directory organization are: * The `coreblocks/params` directory is a mess....
In #547 there is a point: https://github.com/kuznia-rdzeni/coreblocks/blob/757fcd527a5257a25c6202111fd3e237974a9aa1/test/common/profiler.py#L37 I have decided to implement a draft of such operator, but I have some doubts about the semantic. Should we allow changes in...
It is currently artificially limited in CI workflow by `NPROC=1` because of Verilator concurrency issues. File locking approach from #554 could be probably used to fix this issue. It may...
When working on separate project, I noticed that `Connect` does not work as ideal gender-changer - replacing it with calling a constructor passed Method reference from next `Module`, instead of...