coreblocks

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Scheduler name collisions

1

Currently there are three concepts we call *schedulers*: * a hardware module which has an input signal representing a set of requests and an output signal representing which request is...

wikku

More uses of av_comb, slight refactor of RF

1

Probably won't change much, but here we go.

tilk

Implement full `mtval`

1

Implements full `mtval` CSR. Required some tricks. This CSR is optional to fill for all exception types, so if some case becomes too problematic in the future, it can be...

piotro888

Support top-level signals in TransactionComponent

1

`TransactionComponent` only supports connecting nested `Signatures`. It crashes when connecting plain signals (`In`/`Out`) at top level. Amaranth `connect` can be used at higher level to support both cases, it also...

piotro888

icache: support early refill forwarding and lookups on refill

2

Closes #286

piotro888

The circuit generated by `eager_deterministic_cc_scheduler` can be improved a bit. Consider a set of transactions in which every transaction conflicts with every other. This in fact can happen quite often...

xThaid

Here is a PR with implemtation of shift storage to be used in LSU RS. I used hypothesis to do tests and now working with it was much more comfortable...

lekcyjna123

Ordered collections

1

In LSU we are planing to use shift register to keep age order of instructions. Shift registers are linear. Maybe we should consider using the binary trees to keep elements...

lekcyjna123

Implementation of the rounding module for FPU. This module excepts that input is in normalized form (unless the number is subnormal) and, in accordance with RISC-V specification, detects tininess after...

Durchbruchswagen

IOInterface typing wrapper for lib.data signatures

1

Using `amaranth.lib.data` Signatures with typing comes with some boilerplate and repetition :( I came up with a class that can be used both for typing and to get amaranth `Signature`...

piotro888