Krishnan
Krishnan
Already on it :)
Ok, I will look into this
here are my comments: > 1. Is it really a problem, or is it ok to set these properties on all files in the core? So far I have not...
vhdl_parser.py: components should not be converted to lower-case while instantiating Verilog modules
Changing the verilog name to lowercase: - This would be highly difficult while these are vendor/tool-generated models, and changing the case would mean also changing it in each instantiation(s). add_dependency_on...
vhdl_parser.py: components should not be converted to lower-case while instantiating Verilog modules
There is no way to specify in FuseSOC to make a single file dependent on another file(s). However, we can modify the VUnit backend in Edalize to 'enforce' the compile...
I recently realized that the `include_path` is a file-specific property in the CAPI2, which we can exploit for this need. What if we retain this property as file-specific even while...
I agree. For this code, where label1 is an identifier ``` for (i=0; i < width; i=i+1) begin:label1 end ``` We are currently seeing this error: ``` File "/vunit/parsing/tokenizer.py", line...