Neo

support for the xtensa-esp32-elf-g++

3

``` CMAKE_CXX_COMPILER: /opt/xtensa-esp32-elf/bin/xtensa-esp32-elf-g++ CMAKE_CXX_COMPILER_ID: GNU CMAKE_CXX_COMPILER_VERSION: 5.2.0 Boost version: 1.69.0 ``` sml CMakeList.text ``` if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" AND "${CMAKE_CXX_COMPILER_VERSION}" VERSION_LESS 6.0.0) message(FATAL_ERROR "sml requires GCC >= 6.0.0") ``` how to...

fix: should able to declare the input as wire

4

We appreciate your contributing to Verilog-Mode. By contributing you agree this code will be licensed under the GNU Public License. Please check your github name is set to your real...

AUTOINPUT can not create signal with nettype

1

Code snippet like below `/*AUTOINPUT*/` generated like below ``` input a; input [7:0] b; ``` the setting is below ``` verilog-auto-declare-nettype="wire" verilog-auto-wire-type="wire" ``` after some investgation, it seems that when...