Kunlin You

Bump difftest

1

This change will fix missing generated DifftestMacros.v when generating RTL.

We use delayer to delay signal for several cycles. Now we can use Reg or Mem to implement it. In some case like Palladium, Mem will be treated as RAM,...

Trace module will dump trace of IOs between DUT and difftest. With trace file and json profile, we can drive difftest without DUT, which will speed up repeated simulation without...

In Batch DPIC function, some signals, such as coreid/index/address, will serves as buffer locating info, instead of actually trasmitted. So we cluster transmitted data to simplify Parsing logic. Such problem...

Previously, we view data collected from same cycle as a whole, end batch assembling when step data longer than available space. It results in bubble in transmission, and cannot handle...

Delta: support variable elemByteSize

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Previously Delta only supports aligning all the elements in the bundle to a fixed 64-bit size. Since we will later extract the architecture register from the physical register on the...

submodule(difftest): refactor DiffTop, PhyReg and Refill

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Same PR on master: #5188 To fix XSPDB for latest Difftest, we also cherry-pick some PDB-related CI from master.