vhdl-extras
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kevinpt
Flexible VHDL library
May be convenient, for example, when interoperating with code written in Verilog or SystemVerilog, IP cores or other libraries.
This PR contains the following changes: - Bugfix for Xilinx retiming attribute in `pipeline_*` components. The current version uses the attribute name from ISE, which does not support VHDL 2008....
Changes to `change_size` in this PR: - allow an input vector to have any bits direction (`downto` and `to`); - add checks preventing an ill-formed resize operation; - clarify MSB...
This PR redefines resolved arrays as subtypes of the unresolved ones (VHDL-2008 feature). This greatly simplifies type conversions reducing the number of the required functions overloads. The more detailed explanation...
I'm using `reg_file` (in its 2008) version and realised that setting default values isn't straightforward. Imho, adding generics ```vhdl USE_DEFAULT_VALS: boolean := false; DEFAULT_VALS: reg_array; ``` and extending the reset...
