Update pipelining_2008

[oswald3141]

This PR contains the following changes:

• Bugfix for Xilinx retiming attribute in pipeline_* components. The current version uses the attribute name from ISE, which does not support VHDL 2008. The new version replaces it with the name Vivado supports.
• A generic function used for resetting registers in pipeline_* components is replaced with a generic constant containing an empty, resetted element. This approach is more convenient and requires less boilerplate (the function, basically, always contains a definition of a default element anyway). This change breaks compatibility with the current version.
• pipeline_* components now allow to choose between asynchronous and synchronous reset.
• fixed_delay_line_* components now allow to choose a shift registers implementation style (Xilinx only).
• fixed_delay_line_* components now allow to initialize the delay line elements. Since generally initialization decreases a chance of a simulation/hardware mismatch, and cases when it prevents optimizations are rare, the initialization is enabled by default. However, it breaks compatibility with the current version.