vhdl-extras
vhdl-extras copied to clipboard
kevinpt
Flexible VHDL library
The almost full flag in all FIFO should be 1 when there are less elements left than the threshold. That is what the documentation states. There is this check for...
I thought, this version package could benefit from some VHDL-2008 features, such as generic types and functions, unresolved numeric types, and definition of the resolved types as subtypes of the...
I find `resize` function from `numeric_std` a bit confusing. Sometimes I have to take my time to recall, how exactly it performs resizing and which bits are going to be...
Since both, `std_logic_vector`- and `std_ulogic_vector`-related types and functions are present in the package, I guess, the same should apply to the resolved and unresolved versions of `signed` and `unsigned`.
Hi, When compiling the master branch via makefile, the build stops at `rtl/extras_2008/filtering.vhdl` with the following error ```** Error: (vcom-11) Could not find work.pipelining. ###### rtl/extras_2008/filtering.vhdl(345): use extras_2008.pipelining.tapped_delay_line; ** Error...
I tried to use the timing_ops module with GHDL for simulation, but when i try to run the executable with "ghdl -r" command, the following error pops up *bound check...
First, thanks for you work, it's really a big time saver! There's a problem with the way signals are synchronized between read and write clocks in the dual clock FIFO....
Hello Kevin, as GitHub hosts so many awesome lists (Python, Ruby, ...), I thought, we should create a list for VHDL too. I created [awesome-vhdl](https://github.com/VHDL/awesome-vhdl). Please create a pull request...
I'm using an instant of ROM VHDL-2008 on Vivado 2018.3. When I replace a Xilinx xil_defaultlib.ram (by the Block Memory Generator) with extras.rom instance, the design cannot be placed and...
Add an implementation of `tapped_delay_line` which is not present in `pipelining` package. Closes #4. Thanks to @cweickhmann for help and the example of an implementation.