John Wright

@edwardcwang is this still `high priority`? I can't remember if we figured this out.

I'm not sure what this issue is intended to track- are you proposing that in the `auto` mode we turn off clock gating if a technology doesn't have ICG cells?

ok, I think we could do something like ``` if {llength [get_db .base_cells -if {.is_integrated_clock_gating}] > 0} { } ```

This will be useful for allowing tech plugins to have default overrides to hooks/steps.

We have a method of doing relative paths now, so this is not medium priority anymore.

They should probably be `Decimal`s instead of `float`s anyway. We may be able to re-use some of the stuff from the stackup code, or better yet, move everything to hammer...

cc @ssteffl

I don't really see how the firrtl proposal applies here. We already have plans on supporting timing/power analysis within the existing infrastructure. It would be nice to reduce the amount...

Going to do this with #242 Any name preferences? I propose `hier_output_modules` or `hierarchical_output_modules`

We'll revisit this when someone is actually working on FPGA hammer