Joerg-Stephan Vogt comments

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                                            Joerg-Stephan Vogt

AXI4 arlock/awlock has width of 2 bits instead of 1 bit

@ThomasFuchs I know this is no "must fix". What would break if we changed all ports to width 1? Does this have to do with the problem to have "1...

Enable the 2nd DRAM controller for ADKU3 and S121B cards

I don't think we need all combinations (driving someone mad). IMHO the most important option is a) : Provide the full DRAM size, more bandwidth as well. Let the AXI...

Enable the 2nd DRAM controller for ADKU3 and S121B cards

So far, no card implements two DRAM MIGs (with two separate DRAM interfaces in `hardware/hdl/core/psl_fpga_.vhd_source`