Jean-Pierre Thibault

If the project is opened via `cw.open_project()`, then appending or extending its trace set fails silently.

The relative phase between the target clock and the ADC sampling clock phase is not always consistent when `scope.clock.adc_mul` is changed, or when the frequency of `scope.clock.clkgen_src` is changed. Running...

Although Husky's main PLL allows generating clocks down to 500 KHz, currently Husky can only go as low as 5 MHz because this clock feeds other PLLs that are used...