John's Brew

Unexpected behaviour of connections for `Reg` defined within `when` context

4

**Type of issue**: bug report **Impact**: unknown **Development Phase**: request **Other information**: see example below **If the current behavior is a bug, please provide the steps to reproduce the problem:**...

Extmodule port name check fails with length-parameterized Vec ports

2

### Checklist - [x] Did you specify the current behavior? - [x] Did you specify the expected behavior? - [x] Did you provide a code example showing the problem? -...

**Describe the bug** token clean on function return type is probably missing **To Reproduce** function with inner comments **Expected behavior** proper emission of comments

**Describe the bug** Some asTypeOf could be avoided **To Reproduce** - function returns are cast even with the right type - subfields might be cast uselessly **Expected behavior** The right...

**Describe the bug** sv2chisel is too conservative on parenthesis **To Reproduce** `a && b && c` is translated into `(a && b) && c` **Expected behavior** `a && b &&...

Clock is initialized at 1 instead of 0

1

Having main `clock` initialized at `1`instead of `0` will hide underlying issues at `t=0`. We discovered this issue while interconnecting some chisel code using synchronous reset with existing SV blackboxes...

Incorrect BlackBoxes input values changes

9

Hi, I am running into an issue with a simple fallthrough fifo black-boxing. I have a complex module with many fifos which pass successfully its test with verilator. Test crashes...

Fixes

3

Is someone still maintaining this repo ? ### commit 2928469 Fix #56 ### commit 62cbf5f fix another (not raised) issue: trailing parenthesis were colored with the class name #### before...