Johannes Bauer

D-flip-flop is astable when build with subcircuits

3

I'm trying to build a D-flip-flop from SR-flip-flops. I've encapsulated an SR-flipflop as a subckt: ``` $ 0 0.000005 10.20027730826997 50 5 50 5e-11 151 464 576 592 576 0...

Integrity check failed: Data seems to be missing

4

Output of `restic version` -------------------------- restic 0.14.0 compiled with go1.19 on linux/amd64 How did you run restic exactly? ------------------------------- ``` $ time restic prune --repack-small -r restic enter password for...

Expose interface of neutralColor

1

I'm using CircuitJS a lot in lectures I'm giving. One issue that was raised to me is that for people with color deficient vision, colors might not be clearly discernible....

Hello there! I'm using an AQC107 NIC: ``` 01:00.0 Ethernet controller [0200]: Aquantia Corp. AQtion AQC107 NBase-T/IEEE 802.3an Ethernet Controller [Atlantic 10G] [1d6a:07b1] (rev 02) ``` on Linux x86_64 running...