Johann Heyszl

Results 9 comments of Johann Heyszl

[rom,rom_ext] During owner firmware selection/verification handle flash ECC errors as non-fatal

The discussion is currently about option 2 - 'Run w/ ECC and handle fatal alerts somehow'. Option 1 - 'Disabling ECC while reading for hashing+signature verification' was mentioned earlier but...

[rom,rom_ext] During owner firmware selection/verification handle flash ECC errors as non-fatal

thanks @jesultra for stating this so clear: - upon flash error, we can immediately stop verifying, - **but** we want to **stay functional** to try boot the other bank, -...

[tlul] TL-UL `data` zeroing inconsistencies

We have discussed the security implications in the previous issue #16767 and concluded on no HW change for security, but needs to be considered for cryptolib SW dev. Removing Hostlist:Security...

[entropy_src] Restarting physical noise source through rng_en

cc @msfschaffner @andreaskurth

[tlul] tlul_sram_byte data integrity check

Both ways - adding to guidelines, or a modification - sgtm. If the fix is small and we can avoid one more item on the guidelines, that is a benefit....

[hw/kmac] Setup kmac for security verification and check for key leakage from keymgr port

@ballifatih can we please get your opinion on this?

[hw/kmac] Setup kmac for security verification and check for key leakage from keymgr port

@m-temp I see you are familiar with the the block. Would you be interested to review the RTL in the next days to gain some additional assurance here? We are...

[hw/kmac] Setup kmac for security verification and check for key leakage from keymgr port

Thanks @m-temp! The idea is to review the RTL and prob of findings something should be very low, but educated assurance would help to close it :) Ideally this could...

[sival] rv_core_ibex_nmi_irq_test_silicon_owner_sival_rom_ext failure

@moidx thanks for the heads up. IMHO this is OK for the testing we currently do, i.e. not fully invasive and cutting wires.