Jonathan Metter

Xil_DCacheInvalidateRange does not flush aligned ranges shorter than a cacheline anymore

3

The fix in commit https://github.com/Xilinx/embeddedsw/commit/0976d41408dfc4f4cd2be174269fe1ef61176792 changed the behavior of Xil_DCacheInvalidateRange in a way that may or may not have been your intention. Previously, the cortexr5 function performed a flush (clean...