John Martin

Yes, creating a process to change the ISA for the CORE-V extension is a good idea; however, I'm not aware of a ratified, finalized, set in stone specification for the...

@jeremybennett At what point would the ISA need to be frozen to make it into binutils/GCC? From my understanding it must be merged in with the new instruction encoding.

We use an IP-XACT description of the block. We take the FPU, tech libraries, core and debugger and use Git sub modules to link them together. We then treat that...

I haven't looked too close at how the branch is encoded but if you exclude it you *might* be able to squeeze it. It might be a tight fit and...

It should be possible to remap them all. Here is my first attempt at remapping them: [pulp_encoding_blocks.xlsx](https://github.com/openhwgroup/cv32e40p/files/5105416/pulp_encoding_blocks.xlsx) Some notes: * Decoding would start with the block (`custom-0` ... `custom-3`) *...

The encoding isn't really a headache for the hardware. Even before they got swapped around there was some other encodings for some of these instructions. It's more of a headache...

> from "writing" the HW is not a problem, but if the encoding becomes very complicated, the HW complexity increases and the area and timing get worse. But this has...

@craigblackmore Most of `custom-0` and `custom-1` are in use by the post-increment load/store and the immediate branches. Some of the bit manipulation, general ALU and MAC instructions need quite a...

It looks good to me. Thank you for taking the time to optimize the encodings. Will PR #700 include the RTL changes eventually or is it just for the documentation...

So if I implement just the standard stuff (rv32iZicsr) with only machine mode (I may have omitted some other extension or two that was important - sorry if I did)...