jj16791
jj16791
The framework doesn’t seem to recognise the 3rd post-index operand of the ld1r post-index instruction, an example/comparison would be against the correctly disassembled ldrb instruction with post-indexing: ``` ldrb w1,...
Hello, I'm having some issues with running multi-core simulations surrounding atomic memory accesses. I'm currently working with ARM's LLSC instructions and the simulation we're running deadlocks in an infinite access...
In #352, an update was made to address the issue with zero registers as destination operands. Namely, the `results` vector has been modified to include entries for these zero registers...
Supporting single rank MPI codes will help increase the scope of benchmarks supported by SimEng. Running with a single rank should only require MPI system call implementation
Without rebuilding the entire project or forcing a recompile of main.cc, the printed compile date and time doesn't get updated. A likely solution may be to pass the date and...