Jeff Goeders

Add VTR backend

18

I'm working on adding a back-end to run the VTR tool (https://verilogtorouting.org/)

Add VTR backend

8

I'm going to work on running VTR from edalize, and will track progress here. - [x] Arch, channel width (#271) - [ ] Design: including multiple files - [ ]...

Support SystemVerilog using Surelog parser

6

We should be able to handle SystemVerilog input using the Surelog front-end for yosys. * Add a simple regression test to check end-to-end flow. * Update documentation to explain how...

`subs` raises assertion when substituting with constant

2

```python >>> eq = boolean.BooleanAlgebra().parse("A OR (A & ~B)") >>> eq OR(Symbol('A'), AND(Symbol('A'), NOT(Symbol('B')))) >>> eq.subs({boolean.Symbol("B"):True}) Traceback (most recent call last): File "", line 1, in File "/home/jgoeders/bfasst/.venv/lib/python3.10/site-packages/boolean/boolean.py", line 743,...

Distinguishing pins in multi-bit ports

5

If I have a multi-bit port, how do I distinguish between the various pins? I have an 8-bit port called *Din*: When I iterate over the pins they all look...