Jesse C. Lin comments

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                                            Jesse C. Lin

Documents translation (Japanese)

Dear @bmizerany: Sure and I will post a PR after I update the documents, thanks. Jesse

Incorrect initialization with Verilog serializer

In https://github.com/Nic30/hwt/blob/master/hwt/serializer/verilog/serializer.py#L56 line > for i, _v in enumerate(rom.def_val.val): should be change to > for i, _v in enumerate(rom.def_val): ?

Incorrect initialization with Verilog serializer

No hurry, for there is still a lot of fun stuff for us to explore at your great work. Thanks.

Instantiate VHDL or Verilog IPs as black-boxes

Hi Nic30: We need to include some mixed-signal behavioral models in our design, and the first way you mentioned should be OK for our purpose. However, we are still curious...

Native Async reset support in RtlNetlist?

Hi @Nic30: We prefer to reuse the classes defined in hwtLib for ASIC design without manually converting them to an async reset style. If your solution can provide that, it...

Native Async reset support in RtlNetlist?

Hi @Nic30: Great, and it should be able to fulfill our needs; thanks.

Cellgen compact error: can't solve ILP and M5 gate length smaller than tech

Which cell did you select?