Vamsi Vytla

We may have to find another way: https://github.com/enjoy-digital/liteeth/blob/f532a12b40648e84cef626e9343f428e5e366fb4/liteeth/phy/usrgmii.py#L73

A working ping and UDP on both HW and sim on verilator tun/tap over 2 VLAN tags and IPs. See bench/sim_xgmii_vlan.py Currently adding a VLAN tag sets up a new...

litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)

5

Hi All, I am trying to bring up DDR4 on htg-940 board using litedram (I managed to get the spd dump over I2C). I feel like I have made some...

Location of guess-style

2

I am not sure if the following is an issue with emacs-24.4.1 or guess-style. But dropping guess-style/ inside .emacs.d raises the following error upon opening a python file. I moved...

Since we are trying a little to generate xilinx xdc like files from the schematic itself, it would be good to have some signals like FMC names to follow the...