Jeremy Trimble

@Arribas, Thanks for the bug report. I haven't had much time to work on ezdma these days (and in fact I don't have any hardware to test on), but the...

Javi, I haven't used the AXI DMA as of Vivado 2016.2 yet. Not sure if I can help but maybe let me know what version of the xilinx_dma driver you're...

Mike, I think the reasoning for this is because there's no guarantee that the userspace buffer (which appears to be contiguous inside the userspace process's virtual memory) is actually physically...

@gochit, ezdma is designed for use from userspace only, and get_user_pages_fast() is intended only for userspace (process virtual) memory, so I'm not surprised that it's not working when being called...

@gochit: You mentioned that you didn't know how the core's parameters were set when your FPGA image was built -- perhaps as you increase the size of your transfers you...

Hi @noelpedro -- No, it never was. The dmaengine susbsystem maintainer was opposed to the idea. I haven't tried using it in some time but I know some other folks...

I can't be sure but I've seen this sort of thing happen before if your AXI DMA core was configured with a "Width of Buffer Length" register that is too...

@DarrenChengdu, The first things I think of would be: 1. Make sure that the AXI DMA driver is loaded (either compiled into the kernel or added as a module). 2....

@DarrenChengdu, Glad to hear you got it loaded. As for the issue with the loop only executing once -- do you see any complaints from the AXI DMA driver in...

Darren, I'm not sure why the test is only succeeding when the packet size is reduced -- how deep is your FIFO configured in the PL? Performance-wise, the throughput is...