Iztok Jeras

In the [section on EDA tools](https://github.com/pulp-platform/axi#which-eda-tools-are-supported) you could add a suggestion for developers with access to EDA vendor support to report issues with SystemVerilog language support. Open source projects are...

Problems compiling UVVM examples with `llvm` and `gcc` back-ends

6

**Description** I tried to compile three UVVM examples which have scripts for building using GHDL. I can compile them well using the `mcode` backend, but `llvm` and `gcc` back-ends fail...

FPGA synthesis of deep combinational logic (layered barrel shifter implementation)

4

This is not a bug, I would just like to discuss some of my findings. I choose VexRiscv, since it seems to be the the most prominent FPGA implementation of...

The documentation uses the branch name `trunk`, it should be ``. https://github.com/wavedrom/wavedrom/blob/8118f26283e6ecfd4304bdd58103c9621befc6d2/README.md?plain=1#L26

Allow the use of `$` as end of line comment delimiter, in addition to `;`.

1

Skywater PDK spice files are using `$` to add comments ad the end of a command line.

This is not a bug report, I would like some help reading the implementation. I would like to study the data cache and memory controller subsystem. The aim of my...

print formatting of hex numbers, width does not match other simulators

1

While formatting a hex print of a logic vector the width specifier is ignored. My aim was to produce the same string width regardless of the logic vector width. For...

timing against clock falling edge

1

Actually I would like to write about 4 separate issues, but would like to avoid flooding the issue tracker with questions. If you think this should be separate issues I...

Fiting logical operations into LUT4

4

The first commit: - white-space fixes, - Verilog 2001 style parameter definition. Second commit attempts to fit all logical operations into a single LUT4 array. LUT4 has 4 inputs op1,...

`quark` is stuck in an undefined state at reset in simulator with 4-state (`01xz`) support

14

I tried to run a simulation of `femtorv32_quark.v` using the Vivado simulator, because I my SoC gets past synthesis well, but gets minimized to nothing during implementation, I do not...