Iztok Jeras

Commit 4 is again cosmetic. Commit 5 changes the store data encoder, the change reduced the LC count by **2**. Commit 6 fixes the issue with load/store alignment tests. Most...

Internal state register `aluShamt` is missing a reset, causing simulation to fail on `WAIT_ALU_OR_MEM` state. I did not analyze what a random value in `aluShamt` would do. On FPGA this...

`x0` is not initialized to zero, which again would be fine for FPGA, but not for an ASIC. Some FPGA tools allow you to provide the initial value of a...

The `instr` register does not have a reset, which probably should not be an issue. A possible issue is mixing registers with and without reset in the same `always` statement....

First I must say I noticed some [initialization code at the end of the RTL under a BENCH `ifdef`](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v#L381-L387) I did not notice before, this should handle many simulation issues...

Thanks for all the precious details. I still need to read through the SERV documentation, I would like to understand how much is serialized, since probably it is not everything...

Yesterday I wrote a draft spec for a single memory CPU: https://github.com/jeras/rp32/tree/master/hdl/rtl/r5p_1mem At the end is a short comment on handling memory busy with a bus based on tightly integrated...

I already took advantage off all possible combinational bypasses in the draft design. The longest phase sequence is 4 (fetch, rs1 read, rs2 read, write-back for most instructions), and all...

The simplest failing example is `bitvis_uart` compiled with LLVM back-end. It contains two distinct packages named `transaction_pkg` with each of them compiled in its own `work` library. https://github.com/jeras/UVVM/blob/master/bitvis_uart/script/ghdl_compile_all_and_simulate.sh In UVVM...

I found this https://github.com/ghdl/ghdl/issues/539 and this https://github.com/ghdl/ghdl/issues/1622.