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                                            Jenda

Enforce 12 bit range to prevent silent integer overflow

I use the higher bits for synchronization of my T/R switch -- I have extended the internal FPGA FIFO to 13bit and mapped the new bits to Expansion Header and...

Two channel RX with BLADERF_FORMAT_SC16_Q11_META: timestamp increment does no match sample count

I can confirm the issue with both current master and dev-mimo. It does work with FPGA image as of commit b02acdd2d3f7601a550f7c1e7f1943db68c9447e and does not work at a39f691b3a04628a54f1ed0f916e7f42e056f235 (the ones in...