javValverde

Skipping bitstream generation in vivado

8

Is there an option for running vivado without generating a bitstream? This is specially useful when analyzing modules for resource utilization and timing (Hierarchical design UG905)

Create a dependency graph of a big project

3

Hi, I am interested in making a dependency graph of a big project, and I think this tool is a great match for it. Ideally I interface via python with...

As discussed in gitter (sorry I don't know how to link the conversation), I want to know which testbenches depend on some desired VHDL/Verilog files. This code does exactly that,...

Integrate pytest

16

First of all, thanks for this amazing tool. After using it, I cannot think of any other way in which I could write testbenches. I think it is a great...

- Add comments to the multiline regex - Extend unittest for vhdl_parser

I'm using version 0.4.9 and I'm having this surpring behaviour: ```python num = -1.8186004967338193e-16 - 0.99j Fxp(num, dtype="s1.13").uraw() # array(16384.-8110.j) Fxp(num.real, dtype="s1.13").uraw() # array(0) Fxp(num.imag, dtype="s1.13").uraw() # array(8274) ``` Is...