jasonzzzzzzz

cache coherency

2

Hi, I am implement a directory based cache coherency protocol in RTL. I saw OpenPiton github mainpage says the RTL version of cache coherency in OpenPiton is still under developement....

avoid sleeping-relted deadlock (Issue #231)

1

Previous ThreadFini() lacks control of SLEEPING threads in finish(). This change helps many-thread simulation to completion; Otherwise, it deadlocks when running TailBench Apps with only 2-4 threads.

AXI DMA never gives out a ready HIGH

1

I am using AXI DMA and AXI RAM to implement a on-chip RAM accessed through DMA engine. The files I used are axi_dma.v, and axi_ram.v The problem is that I...