Jan Wassenberg

> Wow, I didn't know it was so recent, I had just assumed they'd have produced those variants initially. Hi @mceachen , FYI 128 and 256 bit variants have been...

The CPU/emulator running the test likely doesn't support V extension 1.0 yet, but we are building with flags that allow the compiler to assume that the CPU does support it....

Sounds good, thanks!

That's right, we'd have to see v in the list of isa extensions. I see mention of Sifive bullet from 2020, whereas the V spec was ratified only a few...

Nice, I think the bit we want to test is 1

Yes indeed, you could also write 'V' - 'A' (it is the same). For the patch, we want to also do what was done for Arm ([commit](https://github.com/google/highway/commit/d8867c95df5c5bcd33562b3a24c96f5a54d298a8)). This is a...

Nice, thanks for filing the LLVM issue. For the AT_* values, I simply extrapolated from the fact that RISC-V extensions are (or were mostly) identified with a one-letter name, and...

For HWY_TARGET_STR, this [comment](https://github.com/llvm/llvm-project/issues/56480#issuecomment-1190271810) suggests that arch=rv64gcv1p0 might be exactly what we want.

Thanks for making us aware. This situation is regrettable: an important feature (cycle counter or even timer) has been demoted from the base spec (where it was when I last...

Are we sure about it being the same board? I saw this in the Debian discussion: > - Hifive Unleashed running a 5.10.28 kernel > - Polarfire Icicle running kernel...