Jamie Iles issues

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Results 3 issues of


                                            Jamie Iles

jtag: set output-enable for all bytes.

The official Altera blasters ignore this but the cheap clones require it otherwise everything reads back as zero. Fixes #1 Signed-off-by: Jamie Iles

Instability with clock domain crossing bridge with single clock on Intel FPGA

Synthesizing the USB core with Intel Quartus Prime for a MAX 10 results in enumeration failure with the latest master. I'm using the same 48Mhz clock for clk and clk_48mhz...

Update BRS / TS revision and date for freeze.

Prepare for public review as per https://lf-riscv.atlassian.net/browse/RVS-2155