verilog-hdl topic

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Michaelvll

Verilog modules for beginners

aklsh

FPGA implementation of deflate (de)compress RFC 1950/1951

tomtor

VUnit is a unit testing framework for VHDL/SystemVerilog

VUnit

Various HDL (Verilog) IP Cores

ultraembedded

Python-based Hardware Design Processing Toolkit for Verilog HDL

PyHDI

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

PyHDI

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

NNgen

HDL support for VS Code

mshr-h

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...

sudhamshu091