sdram-controller topic

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

PrimeMHD

SDRAM controller with AXI4 interface

ultraembedded

SDRAM controller optimized to a memory bandwidth of 316MB/s

AngeloJacobo