T. Meissner

icon indicating a website link https://git.goodcleanfun.de icon indicating an email [email protected]

icon location Dresden, Germany icon location FPGA-Engineer doing design and verification using VHDL, SystemVerilog, SVA and PSL.

Results 22 comments of T. Meissner

Not able to compile PSL verification unit file and bind to module.

> vunits aren't yet supported outside synthesis. Oh, in that case I will add a hint to the PSL documentation. The current PSL doc could be the cause that people...

Not able to compile PSL verification unit file and bind to module.

I've updated the [documentation](https://ghdl.readthedocs.io/en/latest/using/ImplementationOfVHDL.html#psl-vunit-files-vhdl-2008-synthesis-only) with information about that vunits are only supported with VHDL-08 & synthesis. See commit 5a5419c.