T. Meissner

Yeah, we also had a similar case in a module which includes some pipelining functionality with various different (complex) types. We can't get it through GHDL synthesis during formal verification....

@bwimm I'm pretty sure that hierarchical names are not supported by GHDL at the moment. Anyway, their use shouldn't cause a GHDL assertion failure.

> Yes, they aren't yet supported, but there is work in progress. Oh, cool, nice to hear :)

@umarcor IIRC, wasn't there a problem with LLVM when files of same name are compiled into the same library? I don't have the issue number at hand, but I remember...

PSL functions like stable() are only implemented for synthesis at the moment. See #1616 Ah, but analyzing should work, so I assume that is an oversight. A workaround I used...

Uh, it's long time ago, that I wrote this code 😄 Do you mean that the memory, needed for the new value, maybe has to allocated new because the new...

Is the basic FSM coverage feature already merged? I don't get any FSm coverage for signals using a enum type like this: ```vhdl type fsm_states is (STATE_IDLE, STATE_TRANSFER_IN, STATE_TRANSFER_OUT); signal...

Mhm, I have similar code and if I remember correctly had to change it. Questa or Synplify (I don't remember which one) didn't compiled it with a similar error. ```vhdl...

@amb5l Ah, okay. Maybe my problematic code was in a different context. I found [LCS2016_072b](http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/LCS2016_072b) which was incorporated in VHDL-19 standard. It adds functionality that `functions` now know the returning...

> Changing `others` to `q'range` fixes the error (thanks for this idea) - but this does suggest that NVC "knows" the range in the context of the procedure and _could_...