Ethan Sifferman

This is the temporary fix I use in my Makefiles: ```Makefile %.netlistsvg.svg: %.json netlistsvg $< -o $@ sed -i -E 's@(]*>)@\1@g' "$@" ```

Is this different from what is provided by `--trace-structs`?

> I'm not sure if having an error output port makes sense for yosys? would we be able to read the calculated value there? Yes! Yosys' eval command calculates the...

I would be happy to make these changes if you think it sounds good

I spent some time sorting through the tests to determine which should be enabled/disabled for Yosys. These should be **modified** for Yosys: * [chapter-11/11.10--string_bit_array-sim.sv](https://github.com/chipsalliance/sv-tests/blob/master/tests/chapter-11/11.10--string_bit_array-sim.sv) * [chapter-12/12.6.1--casex_pattern.sv](https://github.com/chipsalliance/sv-tests/blob/master/tests/chapter-12/12.6.1--casex_pattern.sv) * [chapter-12/12.6.1--casez_pattern.sv](https://github.com/chipsalliance/sv-tests/blob/master/tests/chapter-12/12.6.1--casez_pattern.sv) * [chapter-12/12.6.1--case_pattern.sv](https://github.com/chipsalliance/sv-tests/blob/master/tests/chapter-12/12.6.1--case_pattern.sv)...

I am also encountering this issue. Has anyone had success with using Synopsys tools with this PDK? ## Example I am trying to use sky130 with Design Compiler, but `lc_shell`...

@zachjs Any tips on this? I'd like to have this feature merged soon 😃

> Can you explain why we also add the `synthesis` attributed? From IEC 62142:2005 Section 6.1: > If a synthesis tool supports pragmas to control the structure of the synthesized...

I just ran the following example on Vivado v2019.1, Genus 20.11-s111_1, and DC R-2020.09-SP4: ```verilog module case_test (int2, int1, int0, irq); output int2, int1, int0; input [2:0] irq; reg int2,...

Thanks so much!